Functional Overview

The Power Management Unit (PMU) is responsible for generating all required voltages for different blocks in GR5526. It is optimized for application scenarios with ultra-low power requirements in order to ensure the maximum power efficiency.

In active mode, a DC-DC converter generates voltage for both the transceiver and the DIG_CORE_LDO (LDO) which generates voltage for digital blocks. GR5526 also supports using the DC-DC converter to directly power the digital blocks instead of the DIG_CORE_LDO (LDO). However, since voltage of the transceiver is different from that of the digital blocks, developers need to provide appropriate voltages to different modules. Usually the transceiver requires higher voltage than the digital blocks, so voltage of the DC-DC converter needs to be temporarily increased to meet the voltage requirement of the transceiver when the transceiver is working. The voltage adaptation of the DC-DC converter has already been implemented in the integrated GR5526 SDK.

In order to reduce the power consumption of the chip during sleep, GR5526 uses an LP_LDO to supply its AON modules that stay ON when both the MCU subsystem and the Bluetooth LE subsystem are OFF. The LP_LDO also generates a lower voltage for content retention to the memories where their content is needed after wakeup.

Both the digital voltage and the retention voltage are connected to all power islands through a control switch matrix on the chip.

As shown in 图 8, the GR5526 power architecture is based on the PMU that generates the following supplies from an external supply VBATL.

• IO_LDO: Used to generate the IO voltage to supply the pads of GR5526 and the external devices connecting to GR5526. The IO_LDO is also used to supply power to the stacked Flash.
• VDDIO0: Supply for I/O0 group, connected to stacked Flash and set to voltage required by Flash. This pin requires voltage irrigation, which can be powered by the chip's internal power supply or by an external power supply.
• VDDIO1: Supply for I/O1 group, connected to stacked PSRAM and set to voltage required by PSRAM. This pin requires voltage irrigation, which can be powered by the chip's internal power supply or by an external power supply.
• LP LDO: Supply for AON block, and retention supply for memory instances
• DIG_CORE_LDO: Supply for digital logic blocks
• DC-DC: Supply for RF domain and digital core IDO. Supply for digital logic blocks conditionally.
• EFUSE_LDO: Supply for eFuse programming. eFuse usually needs a high voltage about 2.5 V during programming. DIG_CORE_LDO only controls the digital logic of eFuse.
• VBAT_RF: Usually connected to VBATL
• The USB analog module is powered by a 5 V external power supply through USB_VBUS. The embedded USB LDO converts 5 V to 3.3 V, which is needed for level translation of internal USB differential pair signaling.