Power Management

To minimize power consumption, the GR5526 SoC supports power management in multiple power modes, including active mode, IDLE mode, deep sleep mode, and ultra deep sleep mode.

Cold Boot: Start the MCU from power-off or reset status. Current configuration and data are discarded. Program processing begins again with the initial values.
Warm Boot: Restart the MCU from sleeping. Program processing starts once again where retentive configuration and data are retained.
Check Warm Boot Flag: Whether to enter the warm boot can be judged by the warm boot flag in the SOFTWARE_REG0.Bit[8] register (Address: 0xA000A340).

The power management in different power modes for different modules is shown in 表 32.

表 32 GR5526 power mode management
Module	Software-Configurable Power Modes				Reset Pin Held
Module	Active	IDLE	Deep Sleep	Ultra Deep Sleep	Reset Pin Held
CPU	Active	Off	Off	Off	Off
Flash	On	Standby	Off	Off	Off
SRAM	On	On	Retention	Off	Off
Radio	Available	Available	Off	Off	Off
Supply System	On	On			Off
Current			3.3 μA	1.3 μA	0.15 μA
Register Retention	Full	Full	No	No	No
High-Speed Clock	HFXO_32M or HFRC_192M	HFXO_32M or HFRC_192M	Off	Off	Off
Low-Speed Clock	LFXO_32K or LFRC_32K	LFXO_32K or LFRC_32K	LFXO_32K or LFRC_32K	LFXO_32K or LFRC_32K	Off
Peripherals	Available	Available	Off	Off	Off
PSRAM	Available	Available	Available	Off	Off
Wakeup on RTC	Available	Available	Available	Off	Off
Wakeup on Pin Edge	Available	Available	Available	Available	Off
Wakeup on BLE	Available	Available	Available	Off	Off
Wakeup on USB	Available	Available	Available	Off	Off
Wakeup on Reset Pin	Available	Available	Available	Available	Available
Brown Out Detector (BOD Interrupt)	Active	Active	Off	Off	N/A
Power On Reset (POR)	Active	Active	Active	Active	N/A

Active Mode

The active mode is the default state after power-on reset. In active mode, the Cortex^®-M4F is actively executing code. Active mode supports normal operations of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see 表 32). The power management by the PMU in the active mode is shown in 图 10.

IDLE Mode

In IDLE mode, all unused peripherals can be clocked and no code is executed. The power supply is still applied to the Cortex^®-M4F core logic so that it can immediately become active on a wakeup event and begin executing instructions. The power management by the PMU in the IDLE mode is similar to that in the active mode, as shown in 图 10.

To transition from the Active Mode to IDLE Mode, a specific sequence of instructions is executed on the Cortex^®-M4F core. First, specific bits in the Cortex^®-M4F System Control Register must be set to determine the mode to enter. Refer to The Definitive Guide to Arm Cortex-M3 and Cortex-M4 Processors.

The Cortex^®-M4F core can enter the IDLE state using one of the following 2 methods:

Execute a Wait-For-Interrupt (WFI) instruction.
Execute a Wait-For-Event (WFE) instruction.

Some events will bring the processor back into active mode. The possible reasons to return to Active Mode are:

A reset.
An enabled Interrupt is received by the NVIC.
An event is received by the NVIC.
A Debug Event is received from the DAP.

Deep Sleep Mode

In deep sleep mode, only the always-on (AON) power domain is active. A part of the memory unit is used as retention for storing data that needs to be retained during sleep. Both AON power and retention memory power are supplied from LP_LDO. The power management by the PMU in the deep sleep mode is shown in 图 11.

The sleep request can be initiated by configuring AON_SLP_CTRL. However, before going to sleep, it is necessary to ensure that the device is not in busy state and the remaining sleep time of the system is longer than the sleep threshold. The integrated GR5526 SDK implements pre-sleep state checks and automatic backup of peripheral configurations that need to be preserved before sleep. I/O and MCU peripherals with retention do not need to be reconfigured when being woken up again, and the CPU that continues execution from warm boot goes into active mode.

The I/Os are latched with the value they are in before entering deep sleep mode. This configuration can be achieved by controlling the DPAD_LE_CTRL register. When DPAD_LE_CTRL.DPAD_LE_SLP_VAL = 0 and DPAD_LE_CTRL.DPAD_LE_WKUP_VAL = 1, the I/Os are latched during sleep and automatically unlocked after waking up. If DPAD_LE_CTRL.DPAD_LE_WKUP_VAL = 0, the I/Os can manually be unlocked after waking up by writing ‘1’ to DPAD_LE_CTRL.DPAD_LE_WR_VAL and DPAD_LE_CTRL.DPAD_LE_APPLY in order. This function has been implemented in the SDK. The default configuration in the SDK is DPAD_LE_CTRL.DPAD_LE_SLP_VAL = 0 and DPAD_LE_CTRL.DPAD_LE_WKUP_VAL = 0.

An external wakeup event, RTC Event or BLE Event, is required to bring the SoC back to active mode. For detailed description of the wake-up source, refer to “Wakeup Source”.

The Cortex^®-M4F processor provides a register called the System Control Register (SCR) to allow developers to select between the IDLE mode and deep sleep mode. This register is at an address of 0xE000ED10, and can be accessed in C programming using the “SCB->SCR” symbol. However, the deep sleep mode implementation of the integrated GR5526 SDK has nothing to do with this register. Arbitrary configuration of this register will cause unexpected errors.

AON_SLP_CTRL

Address: 0xA000A43C
Reset Value: 0x00000000

表 33 AON_SLP_CTRL Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R		Reserved bits
8	SLP_DEEP_IN_PROGS	R	0x0	Power controller is processing deep-sleep request.
7:1	RSVD	R		Reserved bits
0	SLP_DEEP_REQ	W	0x0	Write '1' to send sleep request.

DPAD_LE_CTRL

Address: 0xA000A428
Reset Value: 0x00040000

表 34 DPAD_LE_CTRL Register
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R		Reserved bits
18	DPAD_LE_WKUP_VAL	RW	0x1	Set HW controlled DPAD_LE value after waking up. Value: 0x1: The DPAD latch is transparent. 0x0: Latches the pad configurations.
17	RSVD	R		Reserved bit
16	DPAD_LE_SLP_VAL	RW	0x0	Set HW controlled DPAD_LE value during sleep. Value: 0x1: The DPAD latch is transparent. 0x0: Latches the pad configurations.
15:11	RSVD	R		Reserved bits
10	DPAD_LE_CFG_BUSY	R	0x0	DPAD_LE is applying value, do not apply again.
9	RSVD	R		Reserved bit
8	DPAD_LE_RD_VAL	R	0x0	Read the value of DPAD_LE.
7:3	RSVD	R		Reserved bits
2	DPAD_LE_APPLY	W	0x0	Write '1' to apply the value of DPAD_LE_WR_VAL to DPAD_LE control signal.
1	RSVD	R		Reserved bit
0	DPAD_LE_WR_VAL	RW	0x0	Write the value of DPAD_LE.

Ultra Deep sleep mode

Ultra deep sleep mode is the deepest power saving mode that the system can enter. In ultra deep sleep mode, only the always-on (AON) power domain is active. All SRAMs are powered off, so the system restarts execution from cold boot when CPU is woken up from ultra deep sleep mode. The implementation of the system entering ultra deep sleep mode is similar to that in deep sleep mode. The power management by the PMU in ultra deep sleep mode is also similar to that in deep sleep mode, as shown in 图 11.

The I/Os are latched with the value they are in before entering ultra deep sleep mode. This configuration is implemented in the same way as the deep sleep mode.

This mode will block wake-up sources other than AON GPIO peripheral and Sleep timer before going to sleep. Only unmasked wakeup sources can bring the SoC back to active mode. For detailed description of wake-up sources, refer to “Wakeup Source”.