Power Module

DC-DC buck converter provides power to all the RF blocks, digital logic blocks, and memories.

• Designed with soft start so that it can prevent inductor saturation
• Strong loading capability
• Precise Zero Current Detect

By default, the system uses hardware to control signals. In order to improve flexibility, the SoC provides overriding registers to allow software to control signals. The current status of DC-DC converter can be configured by the overriding registers.

• Set the status to the PMU_INTF_OVR_VAL_0.DCDC_EN bit.
• Enable the override function by setting the PMU_INTF_OVR_EN_0.DCDC_EN bit to 1.
• The status of DC-DC converter can be obtained by reading the PMU_INTF_OVR_RD0.DCDC_EN bit.

The voltage of the DC-DC converter can be adjusted by configuring the field DCDC_REG3[7:3] in the RF_REG_1 register. The voltage step is determined by the MSB of the field DCDC_REG3[7:3].

• When the MSB of the field DCDC_REG3[7:3] is 0, the voltage step is 18 mV.
• When the MSB of the field DCDC_REG3[7:3] is 1, the voltage step is 25 mV.

Due to the deviation of the chip process, the voltage step might be slightly different. This norm is for reference only and the voltage step is subject to actual tests.

SYS_LDO provides power to all the RF blocks, digital logic blocks, and memories when the DC-DC converter is disabled. The SYS_LDO can accelerate the transition from sleep mode to active mode.

• Excellent PSRR and low ripple
• Fast startup

By default, the system uses hardware to control signals. In order to improve flexibility, the SoC provides overriding registers to allow software to control signals. The current status of SYS_LDO can be configured by the overriding registers.

• Set the status to the PMU_INTF_OVR_VAL_0.SYS_LDO_EN bit.
• Enable the override function by setting the PMU_INTF_OVR_EN_0.SYS_LDO_EN bit to 1.
• The status of SYS_LDO can be obtained by reading the PMU_INTF_OVR_RD0.SYS_LDO_EN bit.

The SYS_LDO voltage can be adjusted by setting the field FS_REG5[3:0] in the FS_REG_1 register.

CORE_LDO regulates the output of the DC-DC converter or SYS_LDO to supply power to all the digital logic blocks and memory blocks.

• Low voltage drop out
• Supporting bypass mode to adapt to low voltage applications

By default, the system uses hardware to control signals. In order to improve flexibility, the SoC provides overriding registers to allow software to control signals. The current status of CORE_LDO can be configured by the overriding registers.

• Set the status to the PMU_INTF_OVR_VAL_0.DIG_LDO_EN bit.
• Enable the override function by setting the PMU_INTF_OVR_EN_0.DIG_LDO_EN bit to 1.
• The status of CORE_LDO can be obtained by reading the PMU_INTF_OVR_RD0.DIG_LDO_EN bit.

The coarse voltage of CORE_LDO can be adjusted by configuring the field ANACORE_LDO_REG1[5:4] in the RF_REG_4 register. There are four options of the coarse voltage of CORE_LDO as shown in the table below.

The bypass mode can be used to bypass CORE_LDO, allowing the DC-DC converter or SYS_LDO to supply power directly. The RF_REG_4. ANACORE_LDO_REG1[6] can also be used to bypass CORE_LDO. However, If the bypass mode is enabled by setting the ANACORE_LDO_REG1[6] bit, the op-amp circuit of CORE_LDO will be powered off. Therefore, when CORE_LDO exits the bypass mode, it may take more time to restore CORE_LDO.

In addition, when the coarse voltage is selected, the fine voltage can also be configured by the PMU_INTF_OVR_EN_0.AVS_CTL_REF_EN bit and PMU_INTF_OVR_VAL_0.AVS_CTL_REF bit. When the PMU_INTF_OVR_EN_0.AVS_CTL_REF_EN bit is set to 1, the fine voltage value in the PMU_INTF_OVR_VAL_0.AVS_CTL_REF field will take effect.

The voltage of CORE_LDO can also be automatically adjusted by the DDVS in order to meet the lowest power consumption. For detailed information of the DDVS, refer to "Digital Dynamic Voltage Scaling (DDVS)".

The RET_LDO provides the supply voltage to the retention instances of memory when the CORE_LDO is disabled.

• Extra low current consumption
• Stable and reliable for data saving and retention

In sleep mode, RET_LDO is used to provide power for SRAM retention. Typically, the SRAM is powered by CORE_LDO in active mode. When the system enters in sleep mode, the CORE_LDO will usually be turned off, and RET_LDO will be used to power the SRAM. RET_LDO can be enabled or disabled by configuring the LPD_REG1[1] bit in the RF_REG_0 register. RET_LDO is enabled by default. The power-on sequence of RET_LDO refers to "Functional Overview".

In ultra deep sleep mode, because the SRAM does not need to be retained, RET_LDO can be turned off in order to further reduce power consumption.

The voltage of RET_LDO can be adjusted by configuring the field LPD_REG1[4:2] in the RF_REG_0 register. The voltage options of the RET_LDO are shown in the table below.

Appropriately reducing the voltage of RET_LDO can reduce the power consumption in sleep mode. Because RET_LDO is mainly used to maintain SRAM in sleep mode, the voltage of RET_LDO cannot be lower than the retained minimum voltage of the SRAM.

AON_LDO supplies voltage to on the AON domain, including AON I/Os and digital logic blocks.

• 1 mA load current
• Ultra low current consumption

AON_LDO is used to provide power to the AON domain. The voltage of AON_LDO can be configured by setting the field LPD_REG2[6:4] in the RF_REG_0 register, and it should be higher than the digital circuit workable voltage. AON_LDO is the basic supply of the AON domain which is constantly powered on, independently of active mode or any sleep modes. AON_LDO is powered on during the startup period and is unnecessary to be controlled. For the power-on sequence of AON_LDO, refers to "Functional Overview".

The voltage of AON_LDO can be adjusted by configuring the field RF_REG_0.LPD_REG2[6:4]. The voltage options of the AON_LDO are shown in the table below.

Appropriately reducing the voltage of AON_LDO can reduce the power consumption in sleep mode. The voltage of AON_LDO should be higher than the always-on digital circuit workable voltage in order to ensure normal work of the AON domain.

ANA_IO_LDO provides the supply voltage to drive the I/O pads and Flash memories.

• Strong load capability
• Programmable output range

By default, the system uses hardware to control signals. In order to improve flexibility, the SoC provides overriding registers to allow software to control signals. The current status of ANA_IO_LDO can be controlled by the overriding registers.

• Set the status to the PMU_INTF_OVR_VAL_0.IO_LDO_EN bit.
• Enable the override function by setting the PMU_INTF_OVR_EN_0.IO_LDO_EN bit to 1.
• The status of ANA_IO_LDO can be obtained by reading the PMU_INTF_OVR_RD0.IO_LDO_EN bit.

The voltage of ANA_IO_LDO can be adjusted by configuring the field IO_LDO_REG1[6:0] in the RF_REG_0 register. The default voltage of ANA_IO_LDO is set to 1.8 V .

STB_IO_LDO provides the supply voltage to drive the I/O pads during sleep, helping reduce the sleep current.

• Ultra low current consumption
• 1 mA load current
• Programmable output range

By default, the system uses hardware to control signals. In order to improve flexibility, the SoC provides overriding registers to allow software to control signals. The current status of STB_IO_LDO can be controlled by the overriding registers.

• Set the status to the PMU_INTF_OVR_VAL_0.STB_IO_LDO bit.
• Enable the override function by setting the PMU_INTF_OVR_EN_0.STB_IO_LDO bit to 1.
• The status of STB_IO_LDO can be obtained by reading the PMU_INTF_OVR_RD0.STB_IO_LDO bit.

The coarse voltage of STB_IO_LDO can be adjusted by configuring the field LPD_REG61[6:5] in the RF_REG_3 register. The options of the coarse voltage of STB_IO_LDO are shown in the table below. When the coarse voltage is selected, the fine voltage can also be configured by the LPD_REG60[7:4] field in the RF_REG_3 register.