Power Management

By default, the system enters active mode after power-on reset. In active mode, the Cortex^®-M4F is actively executing code. Active mode supports normal operations of the processor and all of the peripherals that are currently available. The radio functionality is available. The system clock can be any available clock source (refer to 表 30). The power management by the PMU in active mode is shown in the figure below. The I/O supply in active mode is from ANA_IO_LDO in order to gain a stronger drive capability.

In IDLE mode, the Cortex^®-M4F core is in sleep mode so that no code is executed. However, the remaining system is fully available. All peripheral functionalities and the radio functionality are still available. The system clock can be any available clock source (refer to 表 30). The power supply is still applied to the Cortex^®-M4F core logic so that it can immediately become active on a wakeup event and begin executing instructions. The power management by the PMU in IDLE mode is similar to that in active mode, as shown in 图 20.

In sleep mode, only the always-on (AON) domain is active. The Cortex®-M4F core is disabled and the radio functionality is not available. The AON domain peripherals are still available, such as AON_WDT, RTC, SLP TIMER and LPCOMP. A part of the memory unit is used as retention for storing data that needs to be retained during sleep. The state of the memory unit during sleep can be controlled by software as described in "SRAM Power Control".

The AON power is supplied from AON_LDO, and the retention memory power is supplied from RET_LDO. The DC-DC convertor, SYS_LDO and CORE_LDO will be powered off. Only low frequency clocks are available in the sleep mode. The I/O supply will be changed from ANA_IO_LDO to STB_IO_LDO in order to reduce power consumption during sleep mode.

The power management by the PMU in sleep mode is shown in the figure below.

The I/Os are latched with the value they are in before the system enters sleep mode. This configuration can be achieved by configuring the DPAD_LE_CTRL register.

• When DPAD_LE_CTRL.SLEEP = 0 and DPAD_LE_CTRL.WAKEUP = 1, the I/Os are latched during sleep and automatically unlocked after wakeup.
• If DPAD_LE_CTRL.WAKEUP = 0, the I/Os can manually be unlocked after wakeup by writing 1 to DPAD_LE_CTRL.WR and DPAD_LE_CTRL.APPLY_WR in order.

This function has been implemented in SDK. The default configuration in the SDK is DPAD_LE_CTRL.SLEEP = 0 and DPAD_LE_CTRL.WAKEUP = 0.

Ultra deep sleep mode is the deepest power saving mode that the system can enter. In this mode, only the always-on (AON) domain is active with limited functionalities. The Cortex^®-M4F core is disabled and the radio functionality is not available. All SRAMs are powered off, so the system restarts execution from cold boot when the system is woken up from ultra deep sleep mode. The power management by the PMU in ultra deep sleep mode is similar to that in sleep mode, as shown in 图 21. RET_LDO can be powered off in ultra deep sleep mode since all SRAMs are not retained.

The I/Os are latched with the value they are in before the system enters ultra deep sleep mode. This configuration is implemented in the same way as the sleep mode.

To transition from active mode to IDLE mode, a specific sequence of instructions is executed on the Cortex®-M4F core. First, specific bits in the Cortex^®-M4F System Control Register must be set to determine the mode to enter. Refer to The Definitive Guide to Arm Cortex-M3 and Cortex-M4 Processors.

The Cortex^®-M4F core can enter the IDLE state using one of the following two methods:

• Execute a Wait-For-Interrupt (WFI) instruction.

• Execute a Wait-For-Event (WFE) instruction.

The sleep request can be initiated by configuring the AON_SLP_CTRL register. However, before the system enters sleep mode, it is necessary to ensure that the device is not in busy state and the remaining sleep time of the system is longer than the sleep threshold. When any high-speed peripherals/radio/DMA is working, or the Flash is being read/written/erased, it indicates the system is in busy state.

The integrated SDK implements pre-sleep state checks and automatic backup of peripheral configurations that need to be retained before the system enters sleep mode. I/O and MCU peripherals with retention do not need to be reconfigured when being woken up again, and the CPU that continues execution from warm boot goes into active mode.

A typical sleep mode entry procedure includes power mode check process and sleep enter process, as shown in the figure below. In the power mode check process, it is mainly to check whether the system can meet the conditions for entering the sleep mode. In the sleep enter process, the current system context should be saved, and then the system can request to enter the sleep mode.

In the sleep enter process, the following operations will be performed:

1. When the PMU receives the sleep request, it will power off all the peripherals and Bluetooth LE Core. If the power- off is successful, the system is able to enter sleep mode. Otherwise, a sleep failure interrupt will be sent to the CPU.
2. Then the system clock is stopped, and both the IO and SRAM will enter retention mode.
3. Subsequently, the MCU core is powered off. The power modules including the DC-DC convertor, SYS_LDO, and CORE_LDO are turned off. High frequency clocks including HFXO_32M, CPLL_192M and HFRC_192M are turned off. The Brown-out Detector (BOD) and Flash are disabled. The I/O supply is changed from ANA_IO_LDO to STB_IO_LDO. After that the ANA_IO_LDO is turned off.

The Cortex^®-M4F processor provides a register called the System Control Register (SCR) to allow developers to select between the IDLE mode and sleep mode. This register is at an address of 0xE000ED10, and can be accessed in C programming using the “SCB->SCR” symbol. However, the sleep mode implementation of the integrated SDK has nothing to do with this register. Arbitrary configuration of this register will cause unexpected errors.

The implementation of the system entering ultra deep sleep mode is similar to that in sleep mode. The difference is that more things will be closed in ultra deep sleep mode before requesting sleep than that in sleep mode. All SRAMs and peripherals will be powered off in order to minimize power consumption. In this mode, AON WDT and RTC will be disabled, and only the sleep timer and AON IO can wakeup the system. The slow frequency clock needs to choose RNG_OSC with div8 in order to minimize power consumption. These operations have been implemented in SDK. Since many states and registers are lost due to power loss, the system will wake up from a cold boot and reinitialize the whole system.

表 31 Power mode entry specifications

Symbol	Description	Min.	Typ.	Max.	Unit
TENT_IDLE	Entry time to IDLE mode		4		cycles
TENT_SLEEP	Entry time to sleep mode		15		cycles
TENT_ULTRA_DEEP_SLEEP	Entry time to ultra deep sleep mode		15		cycles