Functional Description
图 44 depicts the QSPI Controller with the following functions and interfaces:
- APB interface and DMA Controller Interface
- Transmit and receive FIFO controllers and an FSM controller
- Register block
- Shift control and interrupt logic
Transmit and Receive FIFO Buffers
The width of both transmit and receive FIFO buffers is fixed at 32-bit. Data frames that are less than 32 bits must be right-justified when written into the transmit FIFO buffer. The shift control logic automatically right-justifies receive data in the receive FIFO buffer.
Each data entry in the FIFO buffers contains a single data frame. It is not possible to store multiple data frames in a single FIFO location; for example, you may not store two 8-bit data frames in a single FIFO location. If an 8-bit data frame is required, the upper 8-bit of the FIFO entry are ignored or unused when the serial shifter transmits the data.
The transmit FIFO is loaded by writing to the QSPI Controller data register (DATA). Data are popped from the transmit FIFO by the shift control logic into the transmit shift register. The transmit FIFO generates a FIFO empty interrupt request (ssi_txe_intr) when the number of entries in the FIFO is less than or equal to the FIFO threshold value. The threshold value, set through the programmable register TX_FIFO_TL, determines the level of FIFO entries at which an interrupt is generated. The threshold value allows you to provide early indication to the processor that the transmit FIFO is nearly empty. A transmit FIFO overflow interrupt (ssi_txo_intr) is generated if you attempt to write data into an already full transmit FIFO.
Data are popped from the receive FIFO by reading the QSPI Controller data register (DATA). The receive FIFO is loaded from the receive shift register by the shift control logic. The receive FIFO generates a FIFO-full interrupt request (ssi_rxf_intr) when the number of entries in the FIFO is greater than or equal to the FIFO threshold value plus 1. The threshold value, set through programmable register RX_FIFO_TL, determines the level of FIFO entries at which an interrupt is generated.
The threshold value allows you to provide early indication to the processor that the receive FIFO is nearly full. A receive FIFO overrun interrupt (ssi_rxo_intr) is generated when the receive shift logic attempts to load data into a completely full receive FIFO. However, this newly received data is lost. A receive FIFO underflow interrupt (ssi_rxu_intr) is generated if you attempt to read from an empty receive FIFO. This alerts the processor that the read data is invalid.
QSPI Interrupts
The QSPI Controller supports individual interrupt requests, each of which can be masked.
The QSPI Controller interrupts are described as follows:
- Transmit FIFO Empty Interrupt (ssi_txe_intr) – Set when the transmit FIFO is equal to or below its threshold value and requires service to prevent an under-run. The threshold value, set through a software-programmable register, determines the level of transmit FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data is written into the transmit FIFO buffer, bringing it over the threshold level.
- Transmit FIFO Overflow Interrupt (ssi_txo_intr) – Set when an APB access attempts to write into the transmit FIFO after it has been completely filled. When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt clear register (TX_FIFO_OIC).
- Receive FIFO Full Interrupt (ssi_rxf_intr) – Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow. The threshold value, set through a software-programmable register, determines the level of receive FIFO entries at which an interrupt is generated. This interrupt is cleared by hardware when data is read from the receive FIFO buffer, bringing it below the threshold level.
- Receive FIFO Overflow Interrupt (ssi_rxo_intr) – Set when the receive logic attempts to place data into the receive FIFO after it has been completely filled. When set, newly received data is discarded. This interrupt remains set until you read the receive FIFO overflow interrupt clear register (RX_FIFO_OIC).
- Receive FIFO Underflow Interrupt (ssi_rxu_intr) – Set when an APB access attempts to read from the receive FIFO when it is empty. When set, zeros are read back from the receive FIFO. This interrupt remains set until you read the receive FIFO underflow interrupt clear register (RX_FIFO_UIC).
- Multi-Master Contention Interrupt (ssi_mst_intr) –The interrupt is set when another serial master on the serial bus selects the QSPI Controller master as a serial-slave device and is actively transferring data. This informs the processor of possible contention on the serial bus. This interrupt remains set until you read the multi-master interrupt clear register (MULTI_M_IC).
Transfer Modes
When transferring data on the serial bus, the QSPI Controller operates in the modes discussed in this section. The transfer mode (XFE_MODE) is set by writing to control register 0 (CTRL0).
The transfer mode setting does not affect the duplex of the serial transfer. XFE_MODE is ignored for Microwire transfers, which are controlled by the MW_CTRL register.
Transmit
When XFE_MODE = 2‘b01, the receive data is invalid and should not be stored in the receive FIFO. The data transfer occurs as normal, according to the selected frame format (serial protocol). Transmit data is popped from the transmit FIFO and sent through the txd line to the target device, which replies with data on the rxd line. At the end of the data frame, the receive shift register does not load its newly received data into the receive FIFO. The data in the receive shift register is overwritten by the next transfer. You should mask interrupts originating from the receive logic when this mode is entered.
Receive
When XFE_MODE = 2‘b10, the transmit data is invalid. When configured as a slave, the transmit FIFO is never popped in Receive Only mode. The txd output remains at a constant logic level during the transmission. The data transfer occurs as normal according to the selected frame format (serial protocol). The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame. You should mask interrupts originating from the transmit logic when this mode is entered.
Serial Master Operation
Data Transfers
Data transfers are started by the serial-master device. When the QSPI Controller is enabled (SSI_EN = 1), at least one valid data entry is present in the transmit FIFO and a serial-slave device is selected. When actively transferring data, the busy flag (SSI_BUSY) in the status register (STAT) is set. You must wait until the busy flag is cleared before attempting a new serial transfer.
Master SPI and SSP Serial Transfers
When the transfer mode is “transmit and receive” or “transmit only” (XFE_MODE = 2'b00 or XFE_MODE = 2'b01, respectively), transfers are terminated by the shift control logic when the transmit FIFO is empty. For continuous data transfers, you must ensure that the transmit FIFO buffer does not become empty before all the data has been transmitted. The transmit FIFO threshold level (TX_FIFO_TL) can be used to early interrupt (ssi_txe_intr) the processor indicating that the transmit FIFO buffer is nearly empty. When a DMA is used for APB accesses, the transmit data level (DMA_TX_DL) can be used to early request (dma_tx_req) the DMA Controller, indicating that the transmit FIFO is nearly empty. The FIFO can then be refilled with data to continue the serial transfer. The user may also write a block of data (at least two FIFO entries) into the transmit FIFO before enabling a serial slave. This ensures that serial transmission does not begin until the number of data-frames that make up the continuous transfer are present in the transmit FIFO.
When the transfer mode is “receive only” (XFE_MODE = 2'b10), a serial transfer is started by writing one “dummy” data word into the transmit FIFO when a serial slave is selected. The txd output from the QSPI Controller is held at a constant logic level for the duration of the serial transfer. The transmit FIFO is popped only once at the beginning and may remain empty for the duration of the serial transfer. The end of the serial transfer is controlled by the “number of data frames” (NUM_DATA_FRAME) field in control register 1 (CTRL1).
If, for example, you want to receive 24 data frames from a serial-slave peripheral, you should program the NUM_DATA_FRAME field with the value 23; the receive logic terminates the serial transfer when the number of frames received is equal to the NUM_DATA_FRAME value + 1. This transfer mode increases the bandwidth of the APB bus as the transmit FIFO never needs to be serviced during the transfer. The receive FIFO buffer should be read each time the receive FIFO generates a FIFO full interrupt request to prevent an overflow.
When the transfer mode is “eeprom_read” (XFE_MODE = 2‘b11), a serial transfer is started by writing the opcode and/or address into the transmit FIFO when a serial slave (EEPROM) is selected. The opcode and address are transmitted to the EEPROM device, after which read data is received from the EEPROM device and stored in the receive FIFO. The end of the serial transfer is controlled by the NUM_DATA_FRAME field in the control register 1 (CTRL1).
The receive FIFO threshold level (RX_FIFO_TL) can be used to give early indication that the receive FIFO is nearly full. When a DMA is used for APB accesses, the receive data level (DMA_RX_DL) can be used to early request (dma_rx_req) the DMA Controller, indicating that the receive FIFO is nearly full.
DMA Operation
QSPI Controller has a handshaking interface to a DMA Controller to request and control transfers. To enable the DMA Controller interface, User must write the DMA Control Register (DMA_CTRL). Writing a 1 into the TX_DMA_EN bit field of DMA_CTRL register enables the transmit handshaking interface. Writing a 1 into the RX_DMA_EN bit field of the DMA_CTRL register enables the receive handshaking interface.
Transmit Watermark Level
During QSPI serial transfers, transmit FIFO requests are made to the DMA Controller whenever the number of entries in the transmit FIFO is less than or equal to the DMA Transmit Data Level Register (DMA_TX_DL) value; this is known as the watermark level. Then the DMA responds by writing a burst of data to the transmit FIFO buffer, and the length of data is determined by DEST_MSIZE of DMA.
Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers continuously; Otherwise the FIFO could run out of data (underflow). To avoid this situation, the user must set the watermark level correctly.
It is recommended to adhere to the following equation to configure the DMA transmit Operation for QSPI, which help to reduce the number of DMA bursts needed for a block transfer, and improve system utilization.
Receive Watermark Level
During QSPI serial transfers, receive FIFO requests are made to the DMA Controller whenever the number of entries in the receive FIFO is at or above the DMA Receive Data Level Register (DMA_RX_DL+1). This is known as the watermark level. The DMA Controller responds by fetching a burst of data from the receive FIFO buffer, and the length of data is determined by SRC_MSIZE of DMA.
Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continuously. Otherwise, the FIFO will fill with data (overflow). To avoid this situation, the user must set the watermark level correctly.
It is recommended to adhere to the following equation to configure the DMA receive Operation for QSPI, which help to improve system utilization
