Registers

In Master mode

Value:

• 0x1: issues the STOP_DET interrupt only when master is active.
• 0x0: issues the STOP_DET irrespective of whether master is active or not.

This bit controls the generation of the TX_EMPTY interrupt, as described in the RAW_INT_STAT register.

Value:

• 0x0 (DISABLED): Default behavior of TX_EMPTY interrupt
• 0x1 (ENABLED): Controlled generation of TX_EMPTY interrupt

In slave mode

Value:

• 0x0: issues the STOP_DET irrespective of whether it's addressed or not
• 0x1: issues the STOP_DET interrupt only

When it is addressed

• 0x0 (DISABLED): Slave issues STOP_DET interrupt always.
• 0x1 (ENABLED): Slave issues STOP_DET interrupt only if addressed.

Note:

During a general call address, the slave does not issue the STOP_DET interrupt if STOP_DET_INT = 1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR).

This bit controls whether I2C has its slave disabled. By default, the slave is always disabled (in reset state as well). If you need to enable it after reset, set this bit to 0.

If this bit is set (slave is disabled), I2C functions only as a master and does not perform any action that requires a slave.

Note:

Software should ensure that if this bit is written with 0, then bit 0 should also be written with 0.

Value:

• 0x0 (S_EN): Slave mode is enabled.
• 0x1 (S_DIS): Slave mode is disabled.

Determine whether RESTART conditions may be sent when I2C acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions:

• Sending a START BYTE
• Performing any high-speed mode operation
• Performing direction changes in combined format mode
• Performing a read operation with a 10-bit address

By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABORT) of the RAW_INT_STAT register.

Value:

• 0x0 (DISABLED): Master restart disabled
• 0x1 (ENABLED): Master restart enabled

This bit controls whether the I2C starts its transfers in 7-bit or 10-bit addressing mode when I2C acting as a master.

Value:

• 0x0 (ADDR_7BITS): Master 7-bit addressing mode
• 0x1 (ADDR_10BITS): Master 10-bit addressing mode

When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses.

Value:

• 0x0 (ADDR_7BITS): Slave 7-Bit addressing
• 0x1 (ADDR_10BITS): Slave 10-Bit addressing

These bits control at which speed the I2C operates; its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.

This register should be programmed only with a value in the range of 1 to 3.

• 0x1: standard mode (100 kbit/s)
• 0x2: fast mode ( ≤400 kbit/s) or fast plus mode (≤1000 kbit/s)
• 0x3: high-speed mode (2 Mbit/s)

Value:

• 0x1 (STANDARD): Standard Speed mode of operation
• 0x2 (FAST): Fast or Fast Plus mode of operation
• 0x3 (HIGH): High-speed mode of operation

This bit controls whether the I2C master is enabled.

Note:

Software should ensure that if this bit is written with '1', then bit 6 should also be written with '1'.

Value:

• 0x0 (DISABLED): Master mode is disabled
• 0x1 (ENABLED): Master mode is enabled

This bit indicates whether software performs a Device-ID or General Call or START BYTE command.

Value:

• 0x0 (DISABLED): Disable programming of GENERAL_CALL or START_BYTE transmission
• 0x1 (ENABLED): Enable programming of GENERAL_CALL or START_BYTE transmission

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START BYTE command is to be performed by the I2C.

Value:

• 0x0 (GENERAL_CALL): GENERAL_CALL byte transmission
• 0x1 (START_BYTE): START BYTE transmission

This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.

If the TARGET_ADDR and S_ADDR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.

The S_ADDR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only S_ADDR[6:0] is used.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

Note:

The default values cannot be any of the reserved address locations: 0x00 to 0x07, or 0x78 to 0x7F. The correct operation of the device is not guaranteed if you program the S_ADDR or TARGET_ADDR to a reserved value. Refer to 表 85 for a complete list of these reserved values.

This bit field holds the value of the I2C HS mode master code. HS-mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code; up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master.

Value:

• 0x0 (WRITE): Master Write command
• 0x1 (READ): Master Read command

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6.

Note:

This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of COUNT + 10.

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6.

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

The SCL High time depends on the loading of the bus. For 100 pF loading, the SCL High time is 60 ns; for 400 pF loading, the SCL High time is 120 ns.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6.

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160 ns; For 400 pF loading, the SCL low time is 320 ns.

This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

See RAW_INT_STAT for a detailed description of RAW_M_HOLD bit.

Value:

• 0x0 (INACTIVE): RAW_M_HOLD interrupt is inactive
• 0x1 (ACTIVE): RAW_M_HOLD interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RESTART_DET bit.

Value:

• 0x0 (INACTIVE): RAW_RESTART_DET interrupt is inactive
• 0x1 (ACTIVE): RAW_RESTART_DET interrupt is active

See RAW_INT_STAT for a detailed description of RAW_GEN_CALL bit.

Value:

• 0x0 (INACTIVE): RAW_GEN_CALL interrupt is inactive
• 0x1 (ACTIVE): RAW_GEN_CALL interrupt is active

See RAW_INT_STAT for a detailed description of RAW_START_DET bit.

Value:

• 0x0 (INACTIVE): RAW_START_DET interrupt is inactive
• 0x1 (ACTIVE): RAW_START_DET interrupt is active

See RAW_INT_STAT for a detailed description of RAW_STOP_DET bit.

Value:

• 0x0 (INACTIVE): RAW_STOP_DET interrupt is inactive
• 0x1 (ACTIVE): RAW_STOP_DET interrupt is active

See RAW_INT_STAT for a detailed description of RAW_ACTIVITY bit.

Value:

• 0x0 (INACTIVE): RAW_ACTIVITY interrupt is inactive
• 0x1 (ACTIVE): RAW_ACTIVITY interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RX_DONE bit.

Value:

• 0x0 (INACTIVE): RAW_RX_DONE interrupt is inactive
• 0x1 (ACTIVE): RAW_RX_DONE interrupt is active

See RAW_INT_STAT for a detailed description of

RAW_TX_ABORT bit.

Value:

• 0x0 (INACTIVE): RAW_TX_ABORT interrupt is inactive
• 0x1 (ACTIVE): RAW_TX_ABORT interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RD_REQ bit.

Value:

• 0x0 (INACTIVE): RAW_RD_REQ interrupt is inactive
• 0x1 (ACTIVE): RAW_RD_REQ interrupt is active

See RAW_INT_STAT for a detailed description of RAW_TX_EMPTY bit.

Value:

• 0x0 (INACTIVE): RAW_TX_EMPTY interrupt is inactive
• 0x1 (ACTIVE): RAW_TX_EMPTY interrupt is active

See RAW_INT_STAT for a detailed description of RAW_TX_OVER bit.

Value:

• 0x0 (INACTIVE): RAW_TX_OVER interrupt is inactive
• 0x1 (ACTIVE): RAW_TX_OVER interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RX_FULL bit.

Value:

• 0x0 (INACTIVE): RAW_RX_FULL interrupt is inactive
• 0x1 (ACTIVE): RAW_RX_FULL interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RX_OVER bit.

Value:

• 0x0 (INACTIVE): RAW_RX_OVER interrupt is inactive
• 0x1 (ACTIVE): RAW_RX_OVER interrupt is active

See RAW_INT_STAT for a detailed description of RAW_RX_UNDER bit.

Value:

• 0x0 (INACTIVE): RX_UNDER interrupt is inactive
• 0x1 (ACTIVE): RX_UNDER interrupt is active

This bit masks the RAW_GEN_CALL interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): GEN_CALL interrupt is masked
• 0x1 (DISABLED): GEN_CALL interrupt is unmasked

This bit masks the RAW_START_DET interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): START_DET interrupt is masked
• 0x1 (DISABLED): START_DET interrupt is unmasked

This bit masks the RAW_STOP_DET interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): STOP_DET interrupt is masked
• 0x1 (DISABLED): STOP_DET interrupt is unmasked

This bit masks the RAW_ACTIVITY interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): ACTIVITY interrupt is masked
• 0x1 (DISABLED): ACTIVITY interrupt is unmasked

This bit masks the RAW_RX_DONE interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): RX_DONE interrupt is masked
• 0x1 (DISABLED): RX_DONE interrupt is unmasked

This bit masks the RAW_TX_ABORT interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): TX_ABORT interrupt is masked
• 0x1 (DISABLED): TX_ABORT interrupt is unmasked

This bit masks the RAW_RD_REQ interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): RD_REQ interrupt is masked
• 0x1 (DISABLED): RD_REQ interrupt is unmasked

This bit masks the RAW_TX_EMPTY interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): TX_EMPTY interrupt is masked
• 0x1 (DISABLED): TX_EMPTY interrupt is unmasked

This bit masks the RAW_TX_OVER interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): TX_OVER interrupt is masked
• 0x1 (DISABLED): TX_OVER interrupt is unmasked

This bit masks the RAW_RX_FULL interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): RX_FULL interrupt is masked
• 0x1 (DISABLED): RX_FULL interrupt is unmasked

This bit masks the RAW_RX_OVER interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): RX_OVER interrupt is masked
• 0x1 (DISABLED): RX_OVER interrupt is unmasked

This bit masks the RAW_RX_UNDER interrupt in INT_STAT register.

Value:

• 0x0 (ENABLED): RX_UNDER interrupt is masked
• 0x1 (DISABLED): RX_UNDER interrupt is unmasked

Indicate whether the master is holding the bus and TX FIFO is empty.

Value:

• 0x0 (INACTIVE): M_HOLD interrupt is inactive
• 0x1 (ACTIVE): M_HOLD interrupt is active

Indicate whether a RESTART condition has occurred on the I2C interface when I2C is operating in Slave mode and the slave is being addressed.

Note:

However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt.

Value:

• 0x0 (INACTIVE): RESTART_DET interrupt is inactive
• 0x1 (ACTIVE): RESTART_DET interrupt is active

Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the CLR_GEN_CALL register. I2C stores the received data in the RX buffer.

Value:

• 0x0 (INACTIVE): GEN_CALL interrupt is inactive
• 0x1 (ACTIVE): GEN_CALL interrupt is active

Indicate whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.

Value:

• 0x0 (INACTIVE): START_DET interrupt is inactive
• 0x1 (ACTIVE): START_DET interrupt is active

Indicate whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.

In Slave Mode:

• If CTRL[7] = 0x1 (STOP_DET_INT), the STOP_DET interrupt will be issued only if slave is addressed.

Note:

During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_INT = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR).

• If CTRL[7] = 0x0 (STOP_DET_INT), the STOP_DET interrupt is issued irrespective of whether it is being addressed.

In Master Mode:

• If CTRL[10] = 0x1 (STOP_DET_IF_MASTER_ACTIVE), the STOP_DET interrupt will be issued only if Master is active.
• If CTRL[10] = 0x0 (STOP_DET_INT), the STOP_DET interrupt will be issued irrespective of whether master is active or not.

Value:

• 0x0 (INACTIVE): STOP_DET interrupt is inactive
• 0x1 (ACTIVE): STOP_DET interrupt is active

This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it:

• Disabling the I2C
• Reading the CLR_ACTIVITY register
• Reading the CLR_INT register
• System reset

Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus.

Value:

• 0x0 (INACTIVE): ACTIVITY interrupt is inactive
• 0x1 (ACTIVE): ACTIVITY interrupt is active

When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.

Value:

• 0x0 (INACTIVE): RX_DONE interrupt is inactive
• 0x1 (ACTIVE): RX_DONE interrupt is active

This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the TX_ABORT_SRC register indicates the reason why the transmit abort takes place.

Note:

The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the TX_ABORT_SRC register. The TX FIFO remains in this flushed state until the register CLR_TX_ABORT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.

Value:

• 0x0 (INACTIVE): TX_ABORT interrupt is inactive
• 0x1 (ACTIVE): TX_ABORT interrupt is active

This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the DATA_CMD register. This bit is set to 0 just after the processor reads the CLR_RD_REQ register.

Value:

• 0x0 (INACTIVE): RD_REQ interrupt is inactive
• 0x1 (ACTIVE): RD_REQ interrupt is active

The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CTRL register.

• When TX_EMPTY_CTRL = 0:

  This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register.

• When TX_EMPTY_CTRL = 1:

  This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register and the transmission of the address/data from the internal shift register for the most recently popped command is completed.

  It is automatically cleared by hardware when the buffer level goes above the threshold. When EN[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with EN[0] = 0, this bit is set to 0.

Value:

• 0x0 (INACTIVE): TX_EMPTY interrupt is inactive
• 0x1 (ACTIVE): TX_EMPTY interrupt is active

Set during transmit if the transmit buffer is filled to 8 and the processor attempts to issue another I2C command by writing to the DATA_CMD register. When I2C module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared.

Value:

• 0x0 (INACTIVE): TX_OVER interrupt is inactive
• 0x1 (ACTIVE): TX_OVER interrupt is active

Set when the receive buffer reaches or goes above the RX_FIFO_THD threshold in the RX_FIFO_THD register. It is automatically cleared by hardware when buffer level goes below the threshold. If I2C module is disabled (EN[0] = 0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the EN bit 0 is programmed with a 0, regardless of the activity that continues.

Value:

• 0x0 (INACTIVE): RX_FULL interrupt is inactive
• 0x1 (ACTIVE): RX_FULL interrupt is active

Set if the receive buffer is completely filled to 8 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If I2C module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared.

Value:

• 0x0 (INACTIVE): RX_OVER interrupt is inactive
• 0x1 (ACTIVE): RX_OVER interrupt is active

Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared.

Value:

• 0x0 (INACTIVE): RX_UNDER interrupt is inactive
• 0x1 (ACTIVE): RX_UNDER interrupt is active

Receive FIFO Threshold Level.

Control the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in RAW_INT_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer.

A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.

Transmit FIFO Threshold Level.

Control the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in RAW_INT_STAT register).

The valid range is 0 – 255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.

In Master mode:

Value:

• 0x0 (NOT_BLOCKED): TX Command execution not blocked
• 0x1 (BLOCKED): TX Command execution blocked

0x0

When set, the controller initiates the transfer abort.

The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when EN is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the TX FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.

Value:

• 0x0 (DISABLED): ABORT operation not in progress
• 0x1 (ENABLED): ABORT operation in progress

Control whether the I2C is enabled.

Software can disable I2C while it is active. However, it is important that care should be taken to ensure that I2C is disabled properly.

When I2C is disabled, the following occurs:

The TX FIFO and RX FIFO get flushed.

Status bits in the INT_STAT register are still active until I2C goes into IDLE state.

If the I2C module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is completed. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer.

Value:

• 0x0 (DISABLED): I2C is disabled
• 0x1 (ENABLED): I2C is enabled

0x0

Slave Activity Status. When the Slave is not in the IDLE state, this bit is set.

Value:

• 0x0 (INACTIVE): Slave is idle
• 0x1 (ACTIVE): Slave is not idle

0x0

Master Activity Status. When the Master is not in the IDLE state, this bit is set.

Note:

STAT[0], ACTIVITY bit, is the OR of S_ACTIVITY and M_ACTIVITY Y bits.

Value:

• 0x0 (INACTIVE): Master is idle
• 0x1 (ACTIVE): Master not idle

0x0

Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.

Value:

• 0x0 (NOT_FULL): RX FIFO is not full
• 0x1 (FULL): RX FIFO is full

0x0

Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty.

Value:

• 0x0 (EMPTY): RX FIFO is empty
• 0x1 (NOT_EMPTY): RX FIFO not empty

0x1

Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt.

Value:

• 0x0 (NOT_EMPTY): TX FIFO not empty
• 0x1 (EMPTY): TX FIFO is empty

0x1

Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.

Value:

• 0x0 (FULL): TX FIFO is full
• 0x1 (NOT_FULL): TX FIFO not full

I2C Activity Status

Value:

• 0x0 (INACTIVE): I2C is idle
• 0x1 (ACTIVE): I2C is active

This field indicates the number of TX FIFO Data Commands which are flushed due to TX_ABORT interrupt. It is cleared whenever I2C is disabled.

Role of I2C: Master-Transmitter or Slave-Transmitter

This is a master-mode-only bit. Master has detected the transfer abort (EN[1])

Role of I2C: Master-Transmitter

Value:

• 0x0 (ABORT_USER_ABORT_VOID): Transfer abort detected by master- scenario not present
• 0x1 (ABORT_USER_ABORT_GENERATED): Transfer abort detected by master

When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of DATA_CMD register.

Role of I2C: Slave-Transmitter

Value:

• 0x0 (ABORT_SLVRD_INTX_VOID): Slave trying to transmit to remote master in read mode- scenario not present
• 0x1 (ABORT_SLVRD_INTX_GENERATED): Slave trying to transmit to remote master in read mode

This field indicates that a Slave has lost the bus while transmitting data to a remote master. TX_ABORT_SRC[12] is set at the same time.

Note:

Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer owns the bus.

Role of I2C: Slave-Transmitter

Value:

• 0x0 (ABORT_S_ARBLOST_VOID): Slave lost arbitration to remote master- scenario not present
• 0x1 (ABORT_S_ARBLOST_GENERATED): Slave lost arbitration to remote master

This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABORT interrupt to flush old data in TX FIFO.

Role of I2C: Slave-Transmitter

Value:

• 0x0 (ABORT_SLVFLUSH_TXFIFO_VOID): Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
• 0x1 (ABORT_SLVFLUSH_TXFIFO_GENERATED): Slave flushes existing data in TX-FIFO upon getting read command

This field specifies that the Master has lost arbitration, or if TX_ABORT_SRC[14] is also set, then the slave transmitter has lost arbitration.

Role of I2C: Master-Transmitter or Slave-Transmitter

Value:

• 0x0 (ABORT_LOST_VOID): Master or Slave-Transmitter lost arbitration- scenario not present
• 0x1 (ABORT_LOST_GENERATED): Master or Slave-Transmitter lost arbitration

This field indicates that the User tries to initiate a Master operation with the Master mode disabled.

Role of I2C: Master-Transmitter or Master-Receiver

Value:

• 0x0 (ABORT_MASTER_DIS_VOID): User initiating master operation when Master disabled- scenario not present
• 0x1 (ABORT_MASTER_DIS_GENERATED): User initiating master operation when Master disabled

This field indicates that the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the master sends a read command in 10-bit addressing mode.

Role of I2C: Master-Receiver

Value:

• 0x0 (ABRT_10B_RD_VOID): Master not trying to read in 10-bit addressing mode when RESTART disabled
• 0x1 (ABRT_10B_RD_GENERATED): Master trying to read in 10-bit addressing mode when RESTART disabled

To clear Bit 9, the source of the ABORT_SBYTE_NORSTRT must be fixed first; restart must be enabled (CTRL[5]=1), the SPECIAL bit must be cleared (TARGET_ADDR[11]), or the TX_CTRL bit must be cleared (TARGET_ADDR[10]). Once the source of the ABORT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the user is trying to send a START BYTE.

Role of I2C: Master

Value:

• 0x0 (ABORT_SBYTE_NORSTRT_VOID): User trying to send START BYTE when RESTART disabled- scenario not present
• 0x1 (ABORT_SBYTE_NORSTRT_GENERATED): User trying to send START BYTE when RESTART disabled

This field indicates that the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.

Role of I2C: Master-Transmitter or Master-Receiver

Value:

• 0x0 (ABORT_HS_NORSTRT_VOID): User trying to switch Master to HS mode when RESTART disabled- scenario not present
• 0x1 (ABORT_HS_NORSTRT_GENERATED): User trying to switch Master to HS mode when RESTART disabled

This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).

Role of I2C: Master

Value:

• 0x0 (ABORT_SBYTE_ACKDET_VOID): ACK detected for START byte- scenario not present
• 0x1 (ABORT_SBYTE_ACKDET_GENERATED): ACK detected for START byte

This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).

Role of I2C: Master

Value:

• 0x0 (ABRT_HS_ACK_VOID): HS Master code ACKed in HS Mode- scenario not present
• 0x1 (ABRT_HS_ACK_GENERATED): HS Master code ACKed in HS Mode

This field indicates that I2C in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (DATA_CMD[9] is set to 1).

Role of I2C: Master-Transmitter

Value:

• 0x0 (ABORT_GCALL_RD_VOID): GCALL is followed by read from bus-scenario not present
• 0x1 (ABORT_GCALL_RD_GENERATED): GCALL is followed by read from bus

This field indicates that I2C in master mode has sent a General Call and no slave on the bus acknowledged the General Call.

Role of I2C: Master-Transmitter

Value:

• 0x0 (ABORT_GCALL_NOACK_VOID): GCALL not ACKed by any slave-scenario not present
• 0x1 (ABORT_GCALL_NOACK_GENERATED): GCALL not ACKed by any slave

This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).

Role of I2C:Master-Transmitter

Value:

• 0x0 (ABORT_TX_NOACK_VOID): Transmitted data non-ACKed by addressed slave-scenario not present
• 0x1 (ABORT_TX_NOACK_GENERATED): Transmitted data not ACKed by addressed slave

This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.

Role of I2C: Master-Transmitter or Master-Receiver

Value:

• 0x0 (INACTIVE): This abort is not generated
• 0x1 (ACTIVE): Byte 2 of 10-bit Address not ACKed by any slave

This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.

Role of I2C: Master-Transmitter or Master-Receiver

Value:

• 0x0 (INACTIVE): This abort is not generated
• 0x1 (ACTIVE): Byte 1 of 10-bit Address not ACKed by any slave

This field indicates that the Master is in 7-bit address mode and the address sent was not acknowledged by any slave.

Role of I2C: Master-Transmitter or Master-Receiver

Value:

• 0x0 (INACTIVE): This abort is not generated
• 0x1 (ACTIVE): This abort is generated because of NACK for 7-bit address

Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel.

Value:

• 0x0 (DISABLED): Transmit FIFO DMA channel disabled
• 0x1 (ENABLED): Transmit FIFO DMA channel enabled

Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel.

Value:

• 0x0 (DISABLED): Receive FIFO DMA channel disabled
• 0x1 (ENABLED): Receive FIFO DMA channel enabled

ACK General Call. When set to 1, I2C responds with an ACK (by asserting data_oe) when it receives a General Call. Otherwise, I2C responds with a NACK (by negating data_oe).

Value:

• 0x0 (DISABLED): Generate NACK for General Call
• 0x1 (ENABLED): Generate ACK for a General Call

Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of EN from 1 to 0. When read as 1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.

Note:

• If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK transfer, and EN[0] has been set to 0, then this bit is also set to 1.
• When read as 0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.
• The CPU can safely read this bit when EN (bit 0) is read as 0.

Value:

• 0x0 (INACTIVE): Slave RX Data is not lost
• 0x1 (ACTIVE): Slave RX Data is lost

When read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (S_ADDR register) or if the transfer is completed before EN is set to 0 but has not taken effect.

Note:

• If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit will also be set to 1.
• When read as 0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
• The CPU can safely read this bit when EN (bit 0) is read as 0.

Value:

• 0x0 (INACTIVE): Slave is disabled when it is idle
• 0x1 (ACTIVE): Slave is disabled when it is active

EN Status. This bit always reflects the value driven on the output port EN.

When read as 1, I2C is deemed to be in an enabled state.

When read as 0, I2C is deemed completely inactive.

Note:

The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read S_RX_DATA_LOST (bit 2) and S_DIS_BUSY (bit 1).

Value:

• 0x0 (DISABLED): I2C disabled
• 0x1 (ENABLED): I2C enabled

This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic.

This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set.

This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic.

This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set.