ROM Boot

The boot initialization phase mainly initializes the chip to change the chip from limited known state to a more useful known state. This process includes clock initialization, eFuse data reading and configuration, default wake-up source and interrupt priority setting, Flash initialization and OTP initialization.

Because some system-related parameters are stored in eFuse, ROM Boot needs to read the parameters and apply them to the current chip. It includes SWD control, IO LDO trim value, BOD trim value and SRAM control. For the data storage format in eFuse, please refer to "eFuse".

ROM Boot will set a default priority for the interrupts of the chip as described in "Interrupt".

The firmware is usually stored in Flash so that the flash will be initialized in the ROM Boot. This ensures the normal interaction between the chip and the Flash. Because the Flash will be powered off during sleep mode to reduce power consumption, it will be re-initialized during warm boot.

There are two hook functions used for custom code in the ROM Boot. Because the hooks are not registered in the cold boot, they only take effect in warm boot. The two hook functions make customized clock management and register recovery operation possible during warm boot.

In the SoC, some trim parameters are stored in the OTP such as HFRC_192M trim value and Flash timing based on FT trim value as described in "Flash (Non-Volatile Memory)". These parameters will be read out and applied to the SoC during ROM Boot.

Boot Info is a part of the System Configuration Area (SCA), located in the first two sectors of Flash (8 KB in total, 0x0020_0000–0x0020_2000). Boot Info stores the parameters used in the ROM Boot and other system configuration parameters. For detailed structure of the Boot Info, refer to GR533x Developer Guide.

During the Boot Info validation process, some parameters required for basic operation will be verified, such as load address, run address, and firmware size.

The APP verification phase is mainly to preprocess and verify the application firmware to ensure its integrity. The integrity check can be enabled or disabled by configuring the parameters in the Boot Info. Turning off the integrity check can save certain cold boot time. Additionally, if the application firmware is marked to execute on SRAM, the application firmware will be loaded into SRAM.

The Boot Deinitialization phase is mainly to deinitialize modules which are used in ROM Boot and to clean up the environment. During the boot deinitialization phase, the power of the eFuse is turned on. In order to reduce the power consumption, the eFuse will be deinitialized.

There are three target jump modes in ROM Boot, which are XIP mode, Mirror mode and DFU mode.

• In the XIP mode, the ROM Boot will eventually jump to flash address and the code is executed in place.
• In the Mirror mode, the ROM Boot will eventually jump to SRAM address and the code is executed in SRAM.
• In the DFU mode, the ROM Boot will eventually jump to the DFU service.

When the application firmware exists and no exception occurs, ROM Boot will usually jump to the XIP mode or the Mirror mode. Because the SWD interface will be lost during sleep mode, developers can hardly exit sleep mode through reset. Before ROM Boot jumps to the running address, there is a 1s delay to avoid the above situation. This delay can be turned on or off by controlling the parameters in Boot Info.

Exceptions may occur during ROM Boot, causing the chip failing to jump to the application firmware. ROM Boot will record the current execution path to the SOFTWARE_REG1 register. When an exception occurs in ROM Boot, developers can read the SOFTWARE_REG1 register to analyze the cause of the exception. The recorded execution path is shown in the table below.

ROM Boot will also record the current error code to specified SRAM address (0x20001C00). The error code is shown in the table below.

When an exception occurs, Boot ROM will eventually jump into the DFU mode. For detailed information of the DFU mode, refer to GR5xx DFU Development Application Note.